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application note AN262/0189 thermal management in surface mounting the evolutionary trends of integrated circuits and printed circuits boards are, in both cases, towards improved performance and reduced size. from the- se points of view, a factor of major importance has been mutual thermal interaction between ics, even those with low dissipation. it follows then that thermal design of medium and high density applications has evolved to include fac- tors such as power effects, die size, package ther- mal resistance, integration level of active devices and substrate type. added to this a trend towards greater use of switching techniques exists. today, in order to design reliable application cir- cuits, it is necessary to have complete data on pac- kage thermal response characteristics. in fact, it is a well known and long established fact that device lifetime has an exponentialrelationshipwith junction temperature. preliminary considerations heat dissipation for dips with a low thermal conduc- tivity frame (e.g. alloy42) is due to convection and irradiation from an emiting area corresponding to the silicon die and the package die pad. since heat transmission through the lead frame is very poor, dissipation does not depend greatly on substrate type. in fact, samples soldered on printed circuit boards, or inserted in connectors have ne- arly the same dissipation capability as samples su- spended in air. the difference, in the range of just 10%, is commonly ignored and specifications for in- sertion ics only give one thermal resistance value, which is more than adequate for good thermal de- sign. the question then arises, is the approximation valid for so and plcc packages ? the answer is no ! thermal characteristics for these devices are influenced by many factors. 1) device related factors ? size of the dissipating element ? dissipation level ? pulse length and duty cycle 2) package related factors ? thermal conductivity of the frame ? frame design 3) substrate related factors ? thermal conductivity of the substrate ? layout therefore a number of parameters can change the thermal characteristics. these cannot be described by a single thermal resistance, in fact a set of expe- rimental curves gives the best presentation. junction to ambient thermal resistance r th(j-a) r th(j-a) represents the thermal resistance of the sy- stem and comprises the silicon die, the package, and any thermal mass in contact with the package to dissipate heat to the ambient. at a given dissipation level p d , the increase in jun- ction temperature d t j over ambient temperature t a is given by : d t j =r th(j-a) xp d r th(j-a) is made up of many elements both within the device and external to it. if the device is considered alone, r th(j-a) is given by the dissipation path from the silicon die to the lead- frame, to the molding compound, to the ambient. experimental values are very large in this con- dition, especially for small packages such as small outline types. however, this situation is not met in practice and ex- perimental data included in the present work indica- tes the worst case (floating samples). in most applications, surface mount devices are soldered onto a substrate (commonly epoxy glass (fr4) and are in thermal contact with it through the soldered joints and the copper interconnections. in this case, the heat generatedby the active circuit istransferred to the leadframe and then to the substrate. a new dissipation path thus exists in parallel with the pre- vious one whose efficiency depends on the thermal conductivity of the frame and on the length of the printed circuit's copper tracks. figure a shows the experimental module. 1/15
figure a : device soldered to the best board, for junction to ambient thermal resistan- ce measurement. junction to case thermal resis- tance r th(j-c) r th(j-c) is the thermal resistance from the junction to a given area of the peackage's external surface where a heatsink is applied. in signal packages, a suitable area is its upper sur- face. measurements are made with the samples in good thermal contact with an infinite heatsink (fig. b). figure b : junction to case thermal resistance measurement. when a heatsink of thermal resistancer hs is attached to the package, the following relationship is valid : r hs xr * r th(j-a) =r th(j-c) + r hs +r * where r * takesinto account all the other dissipation paths(i.e. junction/frame/substrate).r * is the lowest with low thermal conductivity frames. in high power applications r * or hs and r th(ja) =r th(jc) +r hs junction to pin thermal resistan- ce r th(j-p) in medium power packages r th(j-p) is the thermal re- sistance of the heat transfer leads, from the junction to the external heatsink. in most cases the external heatsink is integrated on the board. figure c shows the experimental setup. figure c : junction to pin thermal resistance measurement. transient thermal resistance for single pulses the electrical equivalent of heat dissipation for a module formed by an active device, its package, a pcb and the ambient, is a chain of rc cells, as shown in fig. d, each with a characteristic rise time ( t ) = rc. figure d : equivalent thermal circuit simplified package. application note 2/15
the thermal capacitance of each cell is a measure of its ability to accumulate heat and depends on the specific heat, volume and density of the constituent materials. when power is switched on, the junction tempera- ture after time it is governed by the heat impedance of the cells, each of which follows its own time con- stant - this is analogous to the exponential charge of rc cells in an electrical circuit. for a pulse lenght t o , the effective t j can be signifi- cantly lower than the steady state t j (fig. e) and the transient thermal resistance r th(to) can be defined from the ratio between the junction temperature at the end of the pulse and the dissipated power. figure e : temperature rise for single power pulse. obviously, this parameter is smaller for shorter pul- ses and higher power can be dissipated without ex- ceeding the maximum junction temperaturedefined from a reliability point of view. the knowledge of transient thermal data is an im- portant tool for cost effectivethermal design of swit- ching applications. peak transient thermal resistan- ce for repeated pulses when pulses of the same height pd are repeated with a duty cycle, dc, and a pulse width t o ,whichis shorter than the overall system time constant, the train of pulses is seen as a continuous source of mean power pd avg ,where: pd avg =pdxdc however the silicon die has a time constant in the order of 1 to 2ms and is able to follow frequencies in the khz range. thus junction temperature oscil- lates about an average value given by : t javg =r th xpd avg as is graphically shown in fig. f. figure f : temperature rise for repeated power pulses. the thermal resistance correspondingto the peak of the steadystate oscillations (peak thermal resis-tan- ce indicates the maximum temperature reached by the junction and, dependingon duty cycle and pulse width, may be much lower than the dc thermal re- sistance. experimental method measurements were performed by means of the especiallydevelopedthermal test patternp432,which is designed according to the semiconductor equip- ment and materials institute (semi) g32 guideline. test chip p432 is based on a dissipating element formed by two npn transistors, eachwith 10w power capability, and one sensing diode (fig. g). the diode is placed on the temperature plateau generated when the two transistors are biased in parallel, and gives the actual junction temperature t j of the dissi- pating element, through the calibration curve (fig. h) of its forward voltage vf versus temperature at a constant current of 100 m a. figure g : thermal test pattern p432. application note 3/15
figure h : calibration curve of p432 tempera- ture sensing diode. transistor size is intentionally limited to 1000sq. mils, in order to simulate high power density, char- acterizing a worst case. die size, which is found to have little influence on thermal resistance when a copper frame is used, is slightly smaller than the die pad size and never exceeds 30k sq mils even in the largest packages such as high pin count plccs. the measurement setup is shown in fig. i. it is com- patible with dc and ac supplies and has an accu- racy of better than 5%. figure i : experimental setup. the advantages offered by the test pattern are : ? high power capability ? repeatable v f and temperature coefficient (1.9mv/c) of the sensing element ? high resolution in pulsed conditions (100 m s) ? better correlation from one package to another. both alloy 42 and copper frames were considered for narrow so packages (150mils body). for wide so (300mils body) and plcc packagesonly copper frames were examined. suitable test boards were developed (figs j, k and l). figure j : test board lay-out for so packages (150 mils body width) board size is : 23 x 42mm 2 . figure k : test board lay-out for so packages (3000 mils body width) board size is 38 x 43mm 2 . figure k : test board for plccs board size is 58 x 58mm 2 . application note 4/15
medium power packages while surface mount signal ics are readily available, almost all power ics are still assembled in traditional insertion packages. medium power sm packages (pd < 2w) can readily be derived from existing small outline and chip car- rier packages by modifying the leadframe - in much the same way that powerdip packageswere derived from standard dips. this approach is particularly attractive because the external dimensions of the package are identical to existing low power packages, allowing the use of standard automatic assembly and test equipment. frame modification is aimed at obtaining a low jun- ction to pin thermal resistance path for the transfer of heat to a suitable external heatsink. a number of leads are connected to the die pad for this purpose. two possibilities are considered here : a medium power plcc44 with 11 heat transfer leads (fig. m) and a medium power so20 with 8 heat transfer le- ads (fig. n). a cost effective heat spreader can be obtained on the board by means of suitably dimensioned copper areas. the heat transfer leads are soldered to there areas (fig. m1, n1). figure m : lead frame for medium power plcc44. figure n : lead frame for medium power so20. figure m1 : test board for medium power plcc44. figure n1 : test board for medium power so20. application note 5/15
thermal data of signal packages summary of junction to ambient thermal resistance in steady state power dissi- pation (sgs-thomson test board) +die size (millinches) +power pd [w] +r th(j-a) [ c/w] on board so8 alloy 42 copper 90 x 100 94 x 125 0.2 0.2 250-310 130-180 so14 alloy 42 copper copper 98 x 100 78 x 118 98 x 125 0.3 0.5 0.7 200-240 120-160 105-145 so16 alloy 42 copper 98 x 118 94 x 185 0.3 0.5 180-215 95-135 so16w copper 120 x 160 0.7 90-112 so20 copper 140 x 220 0.7 77-97 plcc-20 cu 180 x 180 0.7 90-110 plcc-44 cu 260 x 260 1.5 50-60 plcc-68 cu 425 x 425 1.5 40-46 plcc-84 cu 450 x 450 2.0 36-41 r th(j-a) values correspond to low and high board density summary of junction to case thermal resistance +die pad size (millinches) +r th(j-a) [ c/w] plcc20 140 x 140 25 plcc44 260 x 260 13 plcc68 425 x 425 10 plcc84 450 x 450 9 figure 1 : so8. figure 2 : so14. junction to ambient thermal resistance in steady state power dissipa- tion application note 6/15
figure 3 : so16. figure 4 : so20. figure 5 : plcc20. figure 6 : plcc44. figure 7 : plcc68. figure 8 : plcc84. application note 7/15
figure 9 : so16. figure 10 : so20. junction to ambient thermal resistance vs board lay-out (area of copper tracks on the board) figure 11 : plcc44. figure 12 : plcc20. application note 8/15
figure 13 : so8. figure 14 : so14, 16. transient thermal resistance for single pulses figure 15 : so20. figure 16 : plcc44. figure 17 : plcc68. figure 18 : plcc84. application note 9/15
figure 19 : so14. figure 20 : so20. peak transient thermal resistance for repeated pulses figure 21 : plcc44. figure 22 : plcc68. figure 23 : plcc84. application note 10/15
thermal data of medium power packages +r th(j-p) [ c/w] (average) +r th(j-a)* [ c/w] so (12+4+4) 14 50 plcc (33+11) 12 41 * with 6 sq. cm. on board heat-sink. junction to pins thermal resistance vs on die dissipating area figure 24 : so (12 + 4 + 4). figure 25 : plcc (33 + 11). figure 26 : so (12 + 4 + 4). junction to ambient thermal resistance vs area on board heat-sink application note 11/15
figure 27 : plcc (33 + 11). transient thermal resistance for single pulses figure 28 : so (12 + 4 + 4). figure 29 : plcc (33 + 11). pulse length = 0.1 10ms. figure 30 : plcc (33 + 11). pulse length = 1 10s. application note 12/15
figure 31 : plcc (12 + 4 + 4). figure 32 : plcc (33 + 11). peak transient thermal resistance for repeated pulses. application examples of thermal data good thermal design begins with system and relia- bility considerations. this turn is based on correct consideration of ambient and device temperature parameters. the ambient temperature t a defined for applications can range from 50 to 55 c, as is common in many consumer and computer applications, through to 80 c or more in applications such as automotive sy- stems. the ambient temperature depends on the va- rious heat and cooling sources surrounding the device. an important factor in device lifetime is jun- ction temperature - lifetime is approximately halved when junction temperature t j is increased by 10 c. the maximum junction temperature commensurate with good reliability, takes into account the activation energyof the failure mechanisms which may differ for various silicon and packaging tec hnologies. in plasticpackagesthe maximum t jmax is 150 c, but lower values (100 to 120 c) may be specified in high rel applications such as telecoms. when t jmax and t a are known, their difference d t j indicates the permissible junction temeperature rise for a given device. for a given power dissipationpd, the thermal design must ensure that the product pd x rth(j-a) is lower than d t j ; where r th(j-a) is the ther- mal resistance of the device from the junction to the ambient at temperature t a . this takes into conside- ration the many elements connected to the heat source and includes the leadframe, moulding com- pound, substrate and heatsink, if used. example 1 : maximum dissipation for so16 packaged device soldered onto an fr4 board (1 oz copper) under the following conditions : ? ambient temperature : t a =70 c ? maximum junction temperature : t jmax = 130 c the average length of the 12mils wide copper line connected to each pin is 80mils, soldering pads are 30 x 40mils. the total are is thus : a = [(80 x 12) + 1200 x 16] = 34560sq.mils solution from fig. 13, the value for r th(j-a) is 125 c/w for a copper frame package. comparing figs. 5 and 6, a value of about 240 c/w can be assumed for alloy 42 packages. the allowed rise in junction tempera- ture is : d t jmax = 130 - 70 = 60 c maximum dissipation is given by d tjmax/r th(j-a) . therefore : 60/125 = 0.48w for copper frame 60/240 = 0.25 for alloy 42 frame application note 13/15
example 2 : junction temperature for an so20 packaged device soldered on fr4, under the fol- lowing conditions : ? ambient temperature t a =70 c ? dissipated power pd = 0.6w solution a total trace-area of 200k sq.mils is assumed,this then gives, from fig. 14 : ? thermal resistance r th(j-a) =90 c/w ? d t j =pdxr th(j-a) ? d t j = 0.6 x 90 = 54 c ? junction temperature t j =54+70=124 c example 3 : to determine the size of an integra- ted heatsink for a medium power application using a plcc (33 + 11) under the following con- ditions : ? ambient temperature t a =50 c ? max. junction temperature t jmax =150 c ? dissipated power pd = 2.2w solution by calculation the application needs an r th(j-a) of : (150 - 50)/2.2 = 45.5 c/w from figure 32 the on board heatspreader can thus be defined as needing an area of about 2 sq.cm. example 4 : given the application described in example 3 determine the maximum pulse width for a single 4w pulse superimposed on a conti- nuous 1.5w dissipation solution the continuoussteady state junction temperature at 1.5w dissipation is : t jss = (1.5 x 45.5) + 50 = 118.25 c the single pulse is allowed to cause a maximum in- crease of (150 - 118.25 c) = 31.75 c. the related transient thermal resistance is (31.75/4) = 7.9 c/w from figure 33, the corresponding pulse width can be interpreted as being in the order of 200ms. example 5 : in a medium power application using an so (12 + 4 + 4) calculate the average junction temperature and the peak temperature for repeated pulses under the following condi- tions : ? ambient temperature t a =70 c ? on board heatsink area a = 9 sq.cm. ? pulse length = 100ms ? pulse height = 5w ? duty cycle = 20% solution from figure 31, the thermal resistance is found to be 49 c/w. thus the average junction temperature can be calculated : t javg = (5 x 49 x 0.2) + 70 = 119 c from figure 36, the peak thermal resistance is given as around 15 c/w. the peak temperature can thus be calculated as : t p = (5 x 15) + 70 = 145 application note 14/15
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 15/15

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